| 摘要 |
A shared data and clock recovery circuit including a clock synthesizer for generating sampling signals having different phases, a multiple transition detector for receiving a data stream and sampling signals, and for detecting edges in a data stream in response to the sampling signals, a counter and accumulator for detecting the time occurrences and total number of edges, and for performing weighted average calculation to select one of the phases, a decision circuit for detecting the phase difference between a source clock and a local clock such that if the PPM difference between the source clock and the local clock is at least 200 PPM, then selection of a phase is based upon stored historical information, and if the PPM difference between the source clock and the local clock is less than 200 PPM, then selection of a phase is based on a weighted averaging calculation.
|
