| 摘要 |
In a driver circuit of a display device handling a digital image signal, there is provided a driver circuit with a structure in which the timing of holding the image signal in a latch circuit is not influenced by a delay of a sampling pulse. A pre-charge TFT (102) is turned ON in a return line period and an input terminal of a holding portion (101) is set as Hi (VDD). When there is input to all the three signals, the sampling pulse, and a multiplex signal and the digital image signal which are input from the outside, TFTs (104 to 106) all turn ON, and the potential of the input terminal of the holding portion (101) becomes a Lo potential. Thus, holding of the digital image signal is performed. A sampling pulse width is wider than a pulse width of the two signals input from the outside, and the output periods of the two signals input from the outside are completely included in an output period of the sampling pulse. Thus, even if a slight delay is generated, there is no influence on the holding timing, and the holding timing may be easily determined.
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