发明名称 METHOD FOR REDUCING CONTACT RESISTANCE OF SELF-ALIGNED BIT LINE USING TITANIUM-ZIRCONIUM ALLOY SILICIDE
摘要 PURPOSE: A method is provided to reduce contact resistance of a self-aligned bit line by removing a native oxide between an LPC(Landing Poly-plug Contact) and a substrate using a TiZrSi2 layer. CONSTITUTION: An insulating layer(4) with a self-aligned bit line contact is formed on a silicon substrate(1). Titanium and zirconium are deposited on the resultant structure. A TiZrSi2 layer(7) is formed on the exposed silicon substrate in the bit line contact by annealing. A metal nitride layer on the insulating layer is selectively removed by wet-etching. A bit line(8) is then formed by depositing polysilicon on the resultant structure.
申请公布号 KR20040059917(A) 申请公布日期 2004.07.06
申请号 KR20020086422 申请日期 2002.12.30
申请人 HYNIX SEMICONDUCTOR INC. 发明人 CHA, TAE HO
分类号 H01L21/336;(IPC1-7):H01L21/336 主分类号 H01L21/336
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