发明名称 |
Reverse biasing logic circuit |
摘要 |
A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that changes node voltages of the one or more logic transistors between an active mode and a standby mode. During the standby mode, the power source transistor causes reverse biasing of at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the one or more logic transistors.
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申请公布号 |
US6759873(B2) |
申请公布日期 |
2004.07.06 |
申请号 |
US20020153158 |
申请日期 |
2002.05.21 |
申请人 |
THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS |
发明人 |
KANG SUNG-MO;YOO SEUNG-MOON |
分类号 |
H03K19/00;(IPC1-7):H03K19/018 |
主分类号 |
H03K19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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