| 摘要 |
PURPOSE: A power-saving clock signal generation circuit is provided to reduce the unnecessary power consumption due to toggling of an internal clock signal by fixing an internal clock signal to a particular level in a power-down mode. CONSTITUTION: A power-saving clock signal generation circuit includes a clock pad, a counter, and a clock generator. The clock pad(10) is used for outputting selectively pulse signals according to a state of a pad enable signal. The counter(20) is used for preventing a transferring an external clock signal to an internal clock signal during a predetermined period of time when a power-down mode is changed to a normal mode. The clock generator(30) is used for outputting an output signal of the clock pad as the internal clock signal after the predetermined period of time when an external interrupt signal is generated to change the power-down mode to the normal mode.
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