WIRING STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To shield a clock signal line not only in the horizontal direction but also in the vertical direction while suppressing an increase in the area of an integrated circuit and minimizing the deterioration of a wiring property. SOLUTION: A power supply line 15 or a ground line 16 of a reference cell is used as a shield line and the clock signal line 12 and shield lines 11 between which the clock signal line 12 is held are wired in a wiring layer just under the power supply line 15 or the like on a position just under the power supply line 15 or the like. In the case of forming the clock signal line 12 in the lowermost wiring layer or forming a wiring layer under the clock signal line 12, no signal line is wired in an area just under the clock signal line 12. An area of a semiconductor substrate 13 which is under the clock signal line 12 is used for a field oxide film or an element isolation area 17 such as a trench isolation area without using it as a device area such as a transistor. COPYRIGHT: (C)2004,JPO&NCIPI