发明名称 |
SCAN PATH TIMING OPTIMIZER |
摘要 |
PROBLEM TO BE SOLVED: To provide a scan path timing optimizer reducing a wiring jam and occurrence of a hold time error. SOLUTION: A regional connection order decision part 103 decides connection order of a scan path circuit within an area divided by an allocation area division part 102 at random. A regional connection order decision part 104 decides connection order of the scan path circuit between the respective areas so that a wiring length between the areas divided by the allocation area division part 102 is reduced. Therefore, the wiring length between the scan paths can be prolonged locally, and consequently, the wiring jam and the occurrence of the hold time error can be reduced. COPYRIGHT: (C)2004,JPO&NCIPI
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申请公布号 |
JP2004185427(A) |
申请公布日期 |
2004.07.02 |
申请号 |
JP20020352817 |
申请日期 |
2002.12.04 |
申请人 |
RENESAS TECHNOLOGY CORP;MITSUBISHI ELECTRIC ENGINEERING CO LTD |
发明人 |
KANEOKA TOSHIHIRO;TANAKA GENICHI |
分类号 |
G06F17/50;G01R31/3185;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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