发明名称 |
MANAGEMENT OF ARCHITECTURE STATE OF PROCESSOR IN INTERRUPTION |
摘要 |
PROBLEM TO BE SOLVED: To provide a method and system for minimizing a delay when processing an interruption. SOLUTION: This method and system are for managing the hardware architecture state of a processor which is important for executing a process in the processor. When the processor receives the interruption, a shadow copy of the hardware architecture state is stored from the processor into a memory. Since the hardware architecture state can be quickly saved for the interrupted process by the shadow copy of the hardware architecture state, the hardware architecture state of the next process can be soon stored in the processor. COPYRIGHT: (C)2004,JPO&NCIPI
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申请公布号 |
JP2004185602(A) |
申请公布日期 |
2004.07.02 |
申请号 |
JP20030365322 |
申请日期 |
2003.10.24 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
RAVI KUMER ARIMIRRI;CARGNONI ROBERT ALAN;GUY LYNN GUTHRIE;STARKE WILLIAM JOHN |
分类号 |
G06F9/46;G01R31/3185;G06F9/48;G06F12/00;G06F12/08;(IPC1-7):G06F9/46 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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