| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a structure of a memory cell that allows reduction of aspect ratios of the capacitor contact and the bit-line contact and that is less subject to misalignment and less causative of an increase in the number of unrequired processes, and also to provide a method of manufacturing the memory cell. <P>SOLUTION: The method is characterized by steps of: forming element isolation regions to define element regions on a semiconductor substrate; forming transistors provided with respective gate electrodes and source/drain regions on respective element regions; forming first interlayer dielectrics on the element isolation regions and gate electrodes; flattening the first interlayer dielectrics using the gate electrodes as stoppers; forming first contact holes in self-alignment with the gate electrodes on either of the source/drain regions; depositing first conducting layers within the first contact holes and on the gate electrodes; and flattening the first conducting layers using the gate electrodes as stoppers, thereby forming first contact plugs. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
