发明名称 |
METHOD FOR DICING SEMICONDUCTOR WAFER |
摘要 |
PROBLEM TO BE SOLVED: To suppress chip defects by reducing the stress applied to a semiconductor wafer when dicing. SOLUTION: A dicing line 3 surrounding the periphery of each chip region 2 on the semiconductor wafer 1 by drawing a closed loop is provided. Each chip is individually separated from the semiconductor wafer 1 by dicing the semiconductor wafer along the dicing line 3. COPYRIGHT: (C)2004,JPO&NCIPI |
申请公布号 |
JP2004186401(A) |
申请公布日期 |
2004.07.02 |
申请号 |
JP20020351244 |
申请日期 |
2002.12.03 |
申请人 |
FUJITSU LTD |
发明人 |
NISHIMURA TAKAO;KUMAGAI KINICHI |
分类号 |
H01L21/301;(IPC1-7):H01L21/301 |
主分类号 |
H01L21/301 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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