| 摘要 |
PROBLEM TO BE SOLVED: To provide an asynchronous circuit verification support device which uses RTL simulations of high extraction rates to verify an asynchronous circuit between clocks. SOLUTION: The asynchronous circuit verification support device 1 describes the functions of the circuit in RTL, performs logic synthesis for circuit design, and lays out and creates the circuit while using an automatic wiring tool. To simulate the circuit laid out, the support device creates a Key signal and uses the Key signal for processes from describing the functions of the circuit in RTL to the logic design of the circuit to the layout and design of the circuit. Thus, it is made possible to verify the asynchronous circuit between the clocks through the RTL simulation of high extraction rates, to appropriately verify if the arrangement of the circuit can withstand timing violations, while reducing the time of verification by gate simulation. As the operation of the circuit is properly verified, the period of development can be reduced. COPYRIGHT: (C)2004,JPO&NCIPI
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