| 摘要 |
PROBLEM TO BE SOLVED: To automatically adjust latch timing for data, while reducing the number of latch circuits to be provided. SOLUTION: A read controller 104 reads out first check data, which are written in a memory 100, from a check data storage part 102 and then outputs a latch pulse signal s104c to a delay selection part 105. The selection part 105a outputs a delayed pulse signal, with the latch pulse signal s104c being delayed at a leading delay circuit 1051, to a latch circuit 106. The latch circuit 106 latches the check data from the memory 100, when it receives the delayed pulse signal. Subsequently, next data is read out from the memory 100, and the selection part 105a outputs a delayed pulse signal, which is delayed at a delay circuit 1052 located in the following stage, to the latch circuit 106. COPYRIGHT: (C)2004,JPO&NCIPI
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