| 摘要 |
PROBLEM TO BE SOLVED: To provide a scanning test circuit capable of reducing the number of LSI pins, reducing test patterns, improving a failure detection rate, and reducing a scanning test related circuit scale. SOLUTION: This scanning test circuit 10 is characterized by being equipped with a flip-flop 100 having a reset input terminal R for inputting a reset signal RST, for inputting scan data SI and data DI, and acquiring output data DO by switching the inputted scan data and data by a scan shift enable signal SCAN_SE, and an AND gate 101 which is a reset control means for controlling a reset signal by the scan shift enable signal. This constitution has such an effect that the the number of LSI pins can be reduced because test dedicated pins such as pins for scanning test mode input dedicated for a scanning test or for external reset input are not required to be installed separately. COPYRIGHT: (C)2004,JPO&NCIPI
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