| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a duty cycle correction circuit for correcting a duty cycle of an imparted clock to obtain a clock whose duty cycle is 50%. <P>SOLUTION: A duty cycle correction circuit 10A is provided with: a delay part 11A for delaying a clock CK1 to output a clock CK2; and a clock output part 17 composed of transistors 12, 13 with the clocks CK1, CK2 as respective gate inputs, and an inverter circuit 16 for inverting a signal CK3' which is a common drain output of the transistors to output a clock CK3. The delay part 11A delays the clock CK1 so that the falling change of the clock CK1 may appear at a timing of duty cycle 50%. The transistors 12, 13 output a ground voltage and a power supply voltage from their common drain in accordance with the rising change of the clock CK1 and the falling change of the clock CK2 (signal CK3'). The clock CK3 whose duty cycle is finally corrected to about 50% is then obtained. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p> |
