发明名称 |
Frequency detector detecting variation in frequency difference between data signal and clock signal |
摘要 |
A reference clock signal or a clock signal delayed in phase from the clock signal by pi/2 is input to D input terminal of a flip-flop circuit. An FSM receives signals input to the flip-flop circuits and signals which have been held by the flip-flop circuits, and outputs an up signal and a down signal. The flip-flop circuits and the FSM operate in synchronization only with a rising edge of a data signal.
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申请公布号 |
US2004124929(A1) |
申请公布日期 |
2004.07.01 |
申请号 |
US20030442987 |
申请日期 |
2003.05.22 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ISHIWAKI MASAHIKO |
分类号 |
H03K5/26;H03L7/087;H03L7/089;H03L7/091;H03L7/107;H04L7/033;(IPC1-7):H03L7/00 |
主分类号 |
H03K5/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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