发明名称 |
CPU surge reduction and protection |
摘要 |
Methods and systems of providing power to a central processing unit (CPU) provide for enhanced surge protection during CPU current consumption going from high current to low current consumption. In one approach, a circuit as a power output stage with an output node, and a controller circuit coupled to the power output stage. The controller circuit selectively switches the power output stage into a current ramp down mode based on detection of a voltage surge at the output node. The power output stage has an associated current ramp down rate. The CPU is coupled to the output node and a surge notification input of the power output stage, where the power output stage accelerates the current ramp down based on a notification signal from the CPU for a duration proportional to the change in CPU current consumption from high to low current consumption.
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申请公布号 |
US2004125531(A1) |
申请公布日期 |
2004.07.01 |
申请号 |
US20030735674 |
申请日期 |
2003.12.16 |
申请人 |
NGUYEN DON J.;WAIZMAN ALEX |
发明人 |
NGUYEN DON J.;WAIZMAN ALEX |
分类号 |
G06F1/30;(IPC1-7):H02H9/06;H02H3/22 |
主分类号 |
G06F1/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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