发明名称 |
On-chip jitter testing |
摘要 |
On-chip jitter testing includes providing a clock signal to a circuit under test and delaying outputs from the circuit under test by predetermined delay values. For each delay value, a corresponding output from the circuit under test is compared with a reference signal derived from the clock signal to produce a bit error rate count for each delay value. A jitter value in the output of the circuit under test is determined based on the bit error rate counts.
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申请公布号 |
US2004128591(A1) |
申请公布日期 |
2004.07.01 |
申请号 |
US20020331122 |
申请日期 |
2002.12.26 |
申请人 |
IHS HASSAN;ABDENNADHER SALEM |
发明人 |
IHS HASSAN;ABDENNADHER SALEM |
分类号 |
G01R31/317;G01R31/3187;G01R31/3193;(IPC1-7):G06F11/00;G01R31/28 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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