发明名称 |
Semiconductor memory device |
摘要 |
When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ss1 of the driver MOS transistors in the memory cells.
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申请公布号 |
US2004125681(A1) |
申请公布日期 |
2004.07.01 |
申请号 |
US20030733270 |
申请日期 |
2003.12.12 |
申请人 |
YAMAOKA MASANAO;OSADA KENICHI;YANAGISAWA KAZUMASA |
发明人 |
YAMAOKA MASANAO;OSADA KENICHI;YANAGISAWA KAZUMASA |
分类号 |
G11C11/413;G11C11/417;H01L21/8244;H01L27/11;(IPC1-7):G11C5/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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