发明名称 |
METHOD FOR MINIMIZING HUMP IN DEVICE WITH SHALLOW TRENCH ISOLATION STRUCTURE |
摘要 |
PURPOSE: A method is provided to minimize the hump in a device with STI(Shallow Trench Isolation) structure by forming an HLD spacer before gate oxidation processing. CONSTITUTION: A pad pattern is formed on a silicon substrate(100) to expose an isolation region. An STI is formed by etching the exposed isolation region. A gap-fill oxide layer(104) is filled in the STI. The nitride pattern is removed. An HLD spacer(108) is formed at sidewalls of the STI. The first polysilicon layer(110) is formed on an active region(106) between the HLD spacers. The second polysilicon layer(114) is then formed on the first polysilicon layer.
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申请公布号 |
KR20040056967(A) |
申请公布日期 |
2004.07.01 |
申请号 |
KR20020083708 |
申请日期 |
2002.12.24 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
KIM, CHANG HAN |
分类号 |
H01L21/76;(IPC1-7):H01L21/76 |
主分类号 |
H01L21/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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