| 摘要 |
Each memory cell row is associated with access transistors having their source regions electrically connected together by an n<+ >diffusion node extending in the direction of the row. The n<+ >diffusion node is connected to a main word line set to have the low level (a ground voltage) in selecting a corresponding memory cell row. When the main word line is set low, responsively in a data read operation a selected row's word line is set high and in a data write operation a selected row's digit line is set high.
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