| 摘要 |
710,258. Code telegraphy. STANDARD TELEPHONES & CABLES, Ltd. Nov. 2, 1951 [Nov. 8, 1950], No. 27343/50. Class 40 (3) In a telegraph transmission system using code combinations of solely two signalling conditions, e.g. marks and spaces, and such that the code combinations indicate when a character has been incorrectly received, a cross-check combination transmitted after each group of n character code combinations has its elements dependent on the relation between marks and spaces in the correspondingly positioned elements in the combinations of the preceding group, and means at the receiver for scanning the combinations to detect an incorrectly received combination and for examining the cross-check combination to detect the position of an incorrectly received element and means operable on the detection by said examining means of an incorrectly received combination and an incorrectly received element in the same group to correct said element in said combination. Transmitter operation.-Apart from the circuit modification, principally indicated by Fig. 4, to form the cross-check combination at the end of five character-combinations by the addition of the code elements of successive groups represented on a binary scale notation, i.e. mark=0, space=1, the addition of two like elements giving mark and of unlike elements giving rise to space, the transmitting arrangement comprising Figs. 1 to 3 (not shown) is generally similar to that described in Specification 711,901. The circuit, Fig. 4, comprises a chain R4 of cold-cathode discharge tubes 1 to 7 on which the successive steps of obtaining the cross-check combination are recorded, a six-unit counting chain for counting the number of code combinations and a flip-flop F5 employed in connection with the transmitting flip-flop of Fig. 2 (not shown) to carry out the summation of the code combination to be transmitted and the combination so far stored on the cross-check register, R4. At time 6 ms. from the starting of the time cycle, the mark tube M of the flip-flop F5 is fired by a pulse through a gate G38. At 7 ms. the condition of tube 1 of cross-check register R4 is examined by a pulse through gate G35, and if tube 1 is fired, the flipflop F5 is changed over to space by firing of the tube S. At 8 ms. the pattern on R4 is stepped to the right by a pulse through gate G34. At 9 ms. a pulse is applied to gate G31 to examine simultaneously the mark tube M of F5 and the space-tube of the output flip-flop of Fig. 2 (not shown). If both these tubes are fired, gated G31 provides an output via gates G32, G33 to fire tube 7 of the register R4, i.e. a space to represent a mark registered on F5 added to a space on the output flip-flop. At 10 ms. a pulse is applied to a gate G37 to examine the space-tube S of F5 and the space tube of the output flipflop. It both tubes are fired G37 provides an output to refire the mark tube M of flip-flop F5 which records a mark each time a space is added to a space. At 11 ms. the condition of the space-tube S of flip-flop F5 is examined by a pulse applied through a gate G36 and if the space-tube S is still fired, a pulse is applied through G32, G33 to fire tube 7 of the register R4 to record a space on F5 added to a mark on F2, Fig. 2 (not shown), since the fact that F5 is still in the spacing condition implies that the output relay, Fig. 2 (not shown) is still in the marking condition. The auto-transmitter, Fig. 1 (not shown), is arrested at the end of five characters by a counting chain C5, in which the gap 0 is initially fired, so that tube N of flip-flop F4 is fired and passes a potential over lead L1 to the auto-transmitter and to various gates, Figs. 1, 3 (not shown), and indicated at the top of Fig. 4. At the end of five characters gap 5 is fired and the tube C is fired extinguishing the tube N. The auto-transmitter is arrested, and with the removal of potentials from some of the gates, Figs. 1, 3 the compositions of the code combinations on the register, Fig. 1 (not shown) and on register R4 cannot be altered. At the beginning of the next time cycle, the mark tube of the output flip-flop is fired and 0.2 ms. later the space tube S of the flip-flop F5 is examined and if fired it changes the output flip-flop, Fig. 2 (not shown), to space. At 4 ms. gate G40 steps the pattern on R4 and at 6 ms. the mark tube 7 of flip-flop F5 is fired. One ms. later tube 1 is examined, and if fired F5 changes over to space by firing tube S. At 8 ms. the pattern on R4 is again stepped by gate G34. At 20 ms. the mark tube of the output flip-flop is fired and at 20.2 ms. the second element of the cross-check combination is transferred from flip-flop F5 to the output flip-flop. At the end of the cycle a pulse at 138 ms. steps the discharge on chain C5 from gap 5 back to gap O so that the normal tube N is now fired. Receiver arrangement and operation.-A synchronizing or start pulse over lead L14 fires start tube ST of flip-flop F11 to set into operation the timing chain C11, C12, C13, which is of the form generally described in Specification 692,411. The received signals are applied to a thirty-five tube register R12 in a manner similar to that described in Specification 711,901 and the number of spaces in each seven-unit combination is counted by the space counter C18, Fig. 10, the correct number of spaces, i.e. three, leaving the tube 3 unfired, and the counter is reset at 138 ms. During the reception of the code combinations on register R12 and the operation of the counter C18, a counter-check combination is set up on the register R14 operating similarly to the cross-check register R4 of Fig. 4. Additionally, the number of complete combinations received is counted by a chain C17 stepped at 138 ms., i.e. at the end of each cycle, and at the end of five code combinations the firing of gap 5 fires a check-tube C of flip-flop F14 applying a potential to lead L20. During the next cycle of operations, the cross-check combination is received from the transmitter and is compared element by element with the combination set up on R14. At 6 ms. F15 is biased to mark and at 7 ms. is brought back to space if tube 1 of R14 is fired, i.e. if the first element of the counter-check combination is a space. At 8 ms. the pattern on R14 is stepped so that tube 1 now records the second element of the cross-check combination, whilst the first is still registered on F15. At 9 ms. gate G51 opens if the first element of the received combination is space, indicated by potential on lead L15, and if at the same time the first element as recorded by F15 is a mark. An error pulse is passed via gates G51, G52, G59 to lead L22 and there is no potential on lead L19 so that gate G53 is closed. At 10 ms. the incoming space lead is examined by gate G50, and if the first element of the received cross-check combination is a space an input is applied to gate G57. If tube S of flip-flop F15 is a space, i.e. there is agreement, gate G57 passes a pulse through G58 to fire the mark tube of F15. When at 11 ms. G56 examines the condition of F15, the latter will be in mark condition if an incoming space coincides with a space originally applied to F15. If, however, a space registered on F15 coincides with the absence of a space on lead L15, i.e. a mark, F15 will be in the condition with the S tube fired and gate G56 passes an error pulse through gates G52, G59 to lead L22. Reception of signals without error.-If the signals are received without error the arrangement operates generally as described in Specification 711,901, the condition of the tubes 1 to 35 being passed by leads L16, L17 to a flipflop F16, Fig. 11, having mark and space tubes M, S connected to gates G63, G64 and G65, G66, the operative gate being determined by the flipflop F17, brought into operation when, in a code combination, the correction of an element is required. Operation on detection of an error.-If, for example, the counter C18, Fig. 10, detects an incorrect number of spaces in the second received combination, an error pulse is applied to lead L21 at 135 ms. in the second cycle of the time circuit, this lead being connected to tube 5 of the space error register R15, Fig. 11. At time 134 ms. in the third, fourth and fifth cycles the pattern on R15 is stepped to the right and the presence of the error in the second received combination is recorded bv the firing of tube 2 of the register R15. Lead L21 is also connected by lead L31 to a gate G82 which receives a second output from normal tube N of flip-flop F20. When the error pulse appears at 135 ms. in the second cycle it fires " failure tube F of the four-position trigger circuit F19, and at 136 ms. gate G83 allows space-error tube S of flipflop F20 to be fired. If, for example, it is also assumed that the third elements of the received cross-check combination and the derived counter-check combination are in disagreement, an error pulse fed to lead L22 at 49 ms. in the sixth cycle of operations fires tube 7 of check-error register R16 (Fig. 11) the pattern being stepped at 60.6, 80.6, 100.6, 120.6 ms. so that the tube 3 is left fired to indicate that the third element is at fault. A gate G85 is opened via lead L32 and tube S of flip-flop F20 to fire the "correction" tube C of multi-stage trigger F19. At 60 ms. a pulse is applied via gates G86, G87 to refire normal tube N of flip-flop F20 and at 132 ms. to fire the normal tubes N of flip-flop F21, F22, if they are not already fired. At 133 ms. gate G89 fires correction tube C of flip-flop F21 to agree with the fired tube C of the trigger circuit F19, and at 134 ms. gate G90 opens to refire "normal" tube N of the trigger circuit F19. During the next cycle, the first of the five combinations on the register R12, Fig. 9, is read off and passed to the translation circuit, Fig. 13, and the checkerror register R16 is stepped at 0.6, 20.6 . . . 120.6 ms. At 11, |
