发明名称 Pulse width modulation signal generating apparatus having two dead times for on-timings
摘要 In an apparatus for generating complementary first and second pulse width modulation signals (U-PWM, /U-PWM), a signal generating circuit (101, 11U, 21U, 31U, 41U, 101A, 101B, 101C, 51U) generates a first signal for causing the first pulse width signal to switch from an ON level to an OFF level, a second signal for causing the first pulse width signal to switch from the OFF level to the ON level, a third signal for causing the second pulse width signal to switch from the ON level to the OFF level, and a fourth signal for causing the second pulse width signal to switch from the OFF level to the ON level. A control circuit (12, 22, 32, 42, 52) sets a first dead time (d1) between the first and fourth signals and a second time (d2) between the third and second signals individually.
申请公布号 EP1434342(A2) 申请公布日期 2004.06.30
申请号 EP20030090440 申请日期 2003.12.16
申请人 NEC ELECTRONICS CORPORATION 发明人 MITSUKI, JUNKO
分类号 H02M7/48;H02M7/537;H02M7/5387;H02M7/5395;(IPC1-7):H02M7/538 主分类号 H02M7/48
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