| 摘要 |
An object of the present invention is to provide a display device in which a display quality is excellent and a timing margin is large. A signal line driving circuit in a display device has a shift register. Each of the register circuit in the shift register 1 has latch circuits of two stages connected in cascade, an inverter connected to an output terminal of the latch circuit, and clocked inverters connected to an output terminal connected to the inverter. Because the present invention minimizes the number of gate stages from when a start signal is inputted to the shift register, until when the control signal is inputted to analog switches for supplying an analog pixel voltage to the signal lines. Therefore, there is not a likelihood to be influenced by a dispersion of properties of TFTs in the circuits, thereby enlarging an operational margin. Furthermore, because a pulse cut circuit staggers a timing in which the analog switches turn from OFF to ON, there is not a likelihood that the adjacent analog switches turn ON at the same time.
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