Methods and structures for interleavably processing data and error signals in pipelined analog-to-digital converter systems

摘要

Methods and structures are provided for interleavably processing data signals and error signals in alternating first and second operational phases of successive converter stages of pipelined analog-to-digital converter systems. In particular, converter stages are arranged to interleavably process data signals and error signals in alternating first and second operational phases as they convert input data signals to corresponding digital code. The interleaved methods and structures significantly reduce conversion errors caused by less-than-infinite gain A of converter stage amplifiers. Because this performance enhancement is realized primarily with existing pipelined structure, modification complexity and cost of conventional pipelined systems is substantially reduced. The advantages of the invention are also realized with minimal increase in power consumption and circuit space.