| 发明名称 |
Integrated circuit having improved ESD protection |
| 摘要 |
In a high voltage n-channel MOS structure, inserting p+ diffusion and an n-well into NMOS drain area, along with providing ESD protection by means of forming parasitic SCR, allows using signal of 5V and decreases snapback voltage below 2V. |
| 申请公布号 |
US6756642(B2) |
申请公布日期 |
2004.06.29 |
| 申请号 |
US20020291053 |
申请日期 |
2002.11.07 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD |
发明人 |
LEE JIAN-HSING;YU TA-LEE;CHEN SHUI-HUNG |
| 分类号 |
H01L23/58;H01L23/62;H01L27/02;H01L27/082;H01L27/102;H01L29/70;H01L31/11;(IPC1-7):H01L23/62 |
主分类号 |
H01L23/58 |
| 代理机构 |
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代理人 |
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