发明名称 |
Phase lock loop (PLL) apparatus and method |
摘要 |
A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.
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申请公布号 |
US6756828(B2) |
申请公布日期 |
2004.06.29 |
申请号 |
US20020196479 |
申请日期 |
2002.07.17 |
申请人 |
GCT SEMICONDUCTOR, INC. |
发明人 |
LEE KYEONGHO;JEONG DEOG-KYOON |
分类号 |
H03H11/22;H03K9/00;H03L7/089;H03L7/099;H03L7/197;H04B1/28;H04B1/40;(IPC1-7):H03L7/06 |
主分类号 |
H03H11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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