发明名称 |
Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device |
摘要 |
The present invention describes a two transistor flash EEPROM memory cell which has a symmetrical source and drain structure, which permits the cell size not limited by program and erase operations. The memory cell comprises an NMOS floating gate transistor forming a nonvolatile storage device and an NMOS transistor forming an access device. The floating gate transistor is programmed and erased using Fowler-Nordheim channel tunneling. The two transistor memory cell is used in a memory array of columns and rows where a column of cells is coupled by a bit line and a source line, and where a row of cells is coupled by a word line and an access line. The memory array is highly scalable and is targeted for low-voltage, high-speed and high-density programmable logic devices.
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申请公布号 |
US6757196(B1) |
申请公布日期 |
2004.06.29 |
申请号 |
US20010016898 |
申请日期 |
2001.12.14 |
申请人 |
APLUS FLASH TECHNOLOGY, INC. |
发明人 |
TSAO HSING-YA;LEE PETER W.;HSU FU-CHANG |
分类号 |
G11C16/04;H01L27/115;(IPC1-7):G11C16/04 |
主分类号 |
G11C16/04 |
代理机构 |
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地址 |
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