SEMICONDUCTOR MEMORY HAVING VERTICAL CHARGE TRAPPING MEMORY CELLS CAPABLE OF CONTACTING BIT LINES ON GRAVE BOTTOMS AT LOW COST AND MANUFACTURING METHOD THEREOF

摘要

PURPOSE: A semiconductor memory having vertical charge trapping memory cells and a manufacturing method thereof are provided to contact bit lines on grave bottoms at a low cost. CONSTITUTION: A plurality of graves are formed on a semiconductor body or a surface of a substrate with a spacing among them. A memory transistor is disposed on a cell compartment(10). The cell transistor includes a channel region isolated from a gate electrode disposed in the grave. The channel region joins a doped region serving as a source/drain region. A series of memory layers including a first intermediate layer, a memory layer and a second intermediate layer are disposed between the gate electrode and a terminal of either a source or drain of the channel region. The semiconductor body and the source/drain region are interconnected via an upper bit line(15). The graves are alternating between an insulated grave and an active grave. A bit line junction(16) is provided on the upper bit line outside the cell compartment while an additional bit line junction(17) is provided on a lower bit line. The bit line junctions are disposed on sides facing each other.