FLIPFLOP USING COMPLEMENTARY CLOCKING AND PRESCALER USING THE SAME
摘要
PURPOSE: A flipflop using complementary clocking and a prescaler using the same are provided to improve the current driving capacity by using the complementary relation between an NMOS transistor and a PMOS transistor. CONSTITUTION: A first p-type transistor(mp11) is connected between a supply voltage supply unit and the first node to receive data. A second p-type transistor(mp12) is connected between the first and the second nodes to receive the first clock. A first n-type transistor(mn11) is connected between the second node and the ground to receive the data. A third p-type transistor(mp13) is connected between the supply voltage supply unit and the third node. A second n-type transistor(mn12) is connected between the third and the fourth nodes to receive the first clock. A third n-type transistor(mn13) is connected between the fourth node and the ground. A fourth p-type transistor(mp14) is connected between the supply voltage supply unit and an output terminal. A fourth n-type transistor(mn14) is connected between the output terminal and the ground to receive the second clock. A fifth n-type transistor is connected between the first and the second nodes to receive the second clock. A fifth p-type transistor is connected between the third and the fourth nodes to receive the second clock.
申请公布号
KR20040054439(A)
申请公布日期
2004.06.25
申请号
KR20020081477
申请日期
2002.12.18
申请人
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人
HAN, SEON HO;KIM, SEONG DO;PARK, MUN YANG;YOO, HYEON GYU;YOON, YONG SIK