发明名称 |
METHOD FOR MANUFACTURING SHALLOW TRENCH FOR ISOLATION OF SEMICONDUCTOR DEVICE |
摘要 |
PURPOSE: A method for manufacturing a shallow trench for the isolation of a semiconductor device is provided to minimize parasitic capacitance by forming a void in a trench. CONSTITUTION: A pad oxide layer and a nitride layer are sequentially formed on a silicon wafer(10). The first trench is formed for defining an isolation region by selectively etching the nitride layer, the pad oxide layer, and the silicon wafer. The first insulating layer(40) is thickly deposited on the entire surface of the resultant structure. The second trench is formed at the first insulating layer of the first trench. The second trench is transformed into a void(65) by depositing the second insulating layer(70) on the first insulating layer. A planarization is carried out on the resultant structure. Then, the nitride layer is removed by carrying out a cleaning process on the resultant structure.
|
申请公布号 |
KR20040054344(A) |
申请公布日期 |
2004.06.25 |
申请号 |
KR20020081375 |
申请日期 |
2002.12.18 |
申请人 |
ANAM SEMICONDUCTOR., LTD. |
发明人 |
KIM, JAE YEONG |
分类号 |
H01L21/762;(IPC1-7):H01L21/762 |
主分类号 |
H01L21/762 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|