发明名称 VIDEO SIGNAL PROCESSING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a means for preventing chatering due to jitters in selecting a memory on a reading side to avoid address passing when both frequencies are close each other in a circuit to synchronize an input video signal with a synchronous signal, on a display side, to be a reference. SOLUTION: When selecting a reading memory area, an area 1 pulse with a prescribed width by setting a vertical pulse W from a writing address generating part 10 as a start point, and an area 2 pulse with a prescribed width corresponding the maximum jitter amount from an ending point of the area 1 pulse are generated. When a vertical pulse R from a reading address generating part 18 is present within the area 1 pulse, the reading memory area anterio by 1 field from the current writing memory area is selected to be read out, when the vertical pulse R is present within the area 2 pulse, the memory area same as the previous memory area is sequentially selected to be read out. Otherwise, the current writing memory area is selected to be read out. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004177738(A) 申请公布日期 2004.06.24
申请号 JP20020345175 申请日期 2002.11.28
申请人 VICTOR CO OF JAPAN LTD 发明人 IHARA AKINORI
分类号 H04N5/68;G09G5/00;G09G5/397;G09G5/399;(IPC1-7):G09G5/00 主分类号 H04N5/68
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