摘要 |
PROBLEM TO BE SOLVED: To surely transfer start signals between data side drivers connected in cascade manner. SOLUTION: The start signal is supplied in parallel to each data side driver 40. When an enable signal EN is supplied to an input terminal 43 of an initial stage data side driver 40, the start signal is read with an inside start signal read circuit 42, is supplied to a data input terminal (D) of an initial stage flip-flop 45, and is sampled by the rise of the pulse of an inside clock signal CLKB, to successively transfer each flip-flops 45. The enabling signal EN to a next stage data side driver 40 is output to an output terminal 44 from a regular output terminal (Q) of the single-stage flip-flop 45. COPYRIGHT: (C)2004,JPO
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