发明名称 |
Gate-clocked domino circuits with reduced leakage current |
摘要 |
A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.
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申请公布号 |
US2004119503(A1) |
申请公布日期 |
2004.06.24 |
申请号 |
US20020324307 |
申请日期 |
2002.12.18 |
申请人 |
JAMSHIDI SHAHRAM;KUMAR SUDARSHAN |
发明人 |
JAMSHIDI SHAHRAM;KUMAR SUDARSHAN |
分类号 |
H03K19/096;(IPC1-7):H03K19/20 |
主分类号 |
H03K19/096 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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