| 发明名称 |
LOW POWER STATE RETENTION |
| 摘要 |
An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.
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| 申请公布号 |
US2004120182(A1) |
申请公布日期 |
2004.06.24 |
| 申请号 |
US20020329124 |
申请日期 |
2002.12.23 |
| 申请人 |
BIYANI MANISH;CLARK LAWRENCE T.;DEMMONS SHAY P.;RICCI FRANCO |
发明人 |
BIYANI MANISH;CLARK LAWRENCE T.;DEMMONS SHAY P.;RICCI FRANCO |
| 分类号 |
G11C5/14;(IPC1-7):G11C11/00 |
主分类号 |
G11C5/14 |
| 代理机构 |
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