| 发明名称 |
SYNTHESIS OF CYCLIC COMBINATIONAL CIRCUITS |
| 摘要 |
<p>A method for the synthesis of multi-level combinational circuits with cyclic topologies. The techniques, applicable in logic synthesis, and in particular in the structuring phase of logic synthesis, optimize a multi-level description, introducing feedback and potentially optimizing the network.</p> |
| 申请公布号 |
WO2004053742(A1) |
申请公布日期 |
2004.06.24 |
| 申请号 |
WO2003US38622 |
申请日期 |
2003.12.05 |
| 申请人 |
CALIFORNIA INSTITUTE OF TECHNOLOGY;RIEDEL, MARCUS, D.;BRUCK, JEHOSHUA |
发明人 |
RIEDEL, MARCUS, D.;BRUCK, JEHOSHUA |
| 分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
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