| 摘要 |
A method and apparatus for an enhanced parallel port JTAG interface (IEEE Test Access Port) that includes a clock signal line where the clock signal line is a delayed and inverted version of a data strobe signal line. A data input signal line, a data output signal line, a mode select signal line, and a wait signal line are also include. The wait signal line is a delayed and inverted version of the data strobe signal line. The enhanced JTAG cable is connectable between an Enhanced Parallel Port (EPP) and a JTAG port and has increased performance over using a Standard Parallel Port (SPP).
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