| 摘要 |
<p>A method for simulating a chip is provided. The method initiates with defining a library of components (210) for a processor. Then, the interconnections for a set of pipelined processors including the processor are defined. Next, a processor circuit is generated (214) by combining the library components and the interconnections for the set of the pipelined processors. Then , a code representation of a model of the set of pipelined processors is generated. Next, the signals generated by the code representation are compared (216) to the signals generated by the processor circuit. If the comparison of the signals is unacceptable , then the method includes identifying a cause of the unacceptable comparison of the signals at a block level (220) of the processor circuit. A method for generating a netlist for a pipeline of processors, a method for debugging the processor circuit and computer code for simulating a chip circuit are also provided.</p> |
