| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve the problem that the output FP (Flame Pulse) phase of two input interfaces fluctuates. <P>SOLUTION: Each of input interface sections 2<SB>11</SB>, 2<SB>12</SB>is provided with: an extract selection circuit 104 for selecting one of a plurality of input signals led to the input interface sections 2<SB>11</SB>, 2<SB>12</SB>as a synchronizing clock source and transmitting the selected signal as extract selection clocks 220, 219; a selection circuit 105 for selecting either of the extract selection clocks 220, 219 and transmitting the selected clock as a selected output 222; a digital PLL circuit 106 for generating a clock synchronized with the selected output 222 and an FP in an ordinary state and transmitting the result as digital PLL outputs 223, 229; a clock switching circuit 112 for selecting either of the digital PLL outputs 223, 229; and a subordinate control circuit 113 for transmitting a control output 227, wherein the phase of the FP generated by the digital PLL circuit 106 has a phase relation unique to the FP supplied from the first input interface section 2<SB>11</SB>, to the digital PLL circuit 106. <P>COPYRIGHT: (C)2004,JPO |
