| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit capable of synchronizing the phase in a short time without performing excess control of a voltage controlled oscillator even when clock interruption and noise are caused. <P>SOLUTION: The PLL circuit has a VCXO 7 of which the oscillation frequency changes according to the voltage control signal 6, a phase comparator 3 which compares the phases between the leading edges of a reference clock 1 with a prescribed clock cycle inputted from the outside and a clock 2 for transmitting uplink data oscillated from the VCXO 7 by which a phase comparison result is fed back as the voltage control signal 6 and a phase difference detection compensation circuit 10 which judges whether or not phase difference between the reference clock 1 and the clock 2 for transmitting the upward data is smaller than a half of the prescribed clock cycle and forcibly performs control so that the voltage control signal 6 becomes an intermediate potential when this judgment becomes not. <P>COPYRIGHT: (C)2004,JPO |
