| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock front-loading circuit which can be constituted of a logic circuit and in which a delay amount does not have to be adjusted even in a clock signal with a high frequency and even within an error range. <P>SOLUTION: A first delay circuit 10 sequentially delays a clock signal, the level of a clock signal of a corresponding delay output is latched at timing at which the level of the clock signal changes, and a clock signal corresponding to a latch output that stores the level of one side of a change point where one level changes to the other level is decoded at timing when the level of the clock signal next changes. A second delay circuit delays the decoded output minutely to latch the decoded output, and outputs a clock signal corresponding to the latch output that stores the level of one side of the change point where one level changes to the other level as a front-loading clock signal at timing when the level of the clock signal next changes. <P>COPYRIGHT: (C)2004,JPO</p> |
