发明名称 |
Dynamic register with low clock rate testing capability |
摘要 |
A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the output terminal to the input terminal of the circuit element. A control signal is provided to the static loop. The static loop is activated via the control signal to refresh the data in the circuit element. |
申请公布号 |
US2004120203(A1) |
申请公布日期 |
2004.06.24 |
申请号 |
US20030731078 |
申请日期 |
2003.12.09 |
申请人 |
HATAMIAN MEHDI |
发明人 |
HATAMIAN MEHDI |
分类号 |
G01R31/30;G01R31/317;G01R31/3185;H04B3/23;H04B3/32;H04L1/00;H04L1/24;H04L7/02;H04L7/033;H04L25/03;H04L25/06;H04L25/14;H04L25/49;H04L25/497;(IPC1-7):G11C5/00;G11C7/00 |
主分类号 |
G01R31/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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