| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a method of laying out a semiconductor integrated circuit which can reduce the number of designing man-hours. <P>SOLUTION: A reference macro 15 comprises a PLL (phase locked loop) 16 and clock buffers (buffers for sharing in claims) 17 and 18, and has pseudo interconnections 21 and 22 alternative to those corresponding to interconnections of conventional macros 32, 33, and 34 for data communication as shown in the figure. The pseudo interconnections 21 and 22 are wired in such a shape as to allow the agreement between signal delays of macros 1 for data communication located on the right and left sides of the reference macro 15 according to the arrangements of these macros 1 even if the channels of these macros 1 are located. <P>COPYRIGHT: (C)2004,JPO</p> |
