发明名称 CACHE CONTROLLER, CACHE CONTROL METHOD, COMPUTER SYSTEM
摘要 PROBLEM TO BE SOLVED: To eliminate possibility that the cash hit ratio of a task is lowered owing to processing of another task in a computer system having a microprocessor which performs parallel processing of a plurality of tasks, a cache memory and a main memory. SOLUTION: A cache controller 1 is provided with: an area management part 12 which manages tasks to which the microprocessor applies the parallel processing and the areas formed by dividing the memory area of a cache memory 2 by associating the tasks and the areas; an address decomposition part 14 which accepts and decomposes an address transmitted from the microprocessor in a process of a certain task of the microprocessor; and a caching part which acquires from the main memory a group of data by the unit of blocks including data existing in the accepted address and stores the group of data in an area associated with the tasks when a tag generated by address decomposition is not associated and recorded in a cache directory 17. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004178571(A) 申请公布日期 2004.06.24
申请号 JP20030376178 申请日期 2003.11.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MORISHITA HIROYUKI;KIYOHARA TOKUZO
分类号 G06F12/08;(IPC1-7):G06F12/08 主分类号 G06F12/08
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