发明名称 MEMORY APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a memory apparatus which can suppress the decrease of readout margin due to fluctuation in reference potential while reducing the area of a memory cell array. SOLUTION: The memory apparatus is provided with a ferroelectric capacitor 12 having a hysteresis characteristic and a read amplifier 7 which impresses a bias voltage to directions varying in the first time and the second time to the ferroelectric capacitor 12 in reading out data and decides the readout data by comparing the readout data of the first time and the readout data of the second time. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004178734(A) 申请公布日期 2004.06.24
申请号 JP20020345580 申请日期 2002.11.28
申请人 SANYO ELECTRIC CO LTD 发明人 TAKANO HIROSHI
分类号 G11C11/22;(IPC1-7):G11C11/22 主分类号 G11C11/22
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