发明名称 |
Single ended clock signal generator having a differential output |
摘要 |
Embodiments of the present invention provide for generating a sampled differential pattern signal with reduced jitter. In one embodiment of the present invention, a seed frequency generator provides a differential seed frequency signal. The differential seed frequency signal is converted to a single ended seed frequency signal by a differential-to-single ended converter. The pattern generation logic utilizes the single end seed frequency signal to generate single ended pattern signals. Single ended-to-differential samplers then generate a sampled differential pattern signal by sampling the single ended pattern signal according to the differential seed frequency signal.
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申请公布号 |
US2004119509(A1) |
申请公布日期 |
2004.06.24 |
申请号 |
US20020327217 |
申请日期 |
2002.12.20 |
申请人 |
RICHMOND GREG;AKYILDIZ AHMET;SHKIDT ALEX |
发明人 |
RICHMOND GREG;AKYILDIZ AHMET;SHKIDT ALEX |
分类号 |
G05F1/04;H03K3/00;H03K5/151;H03L;(IPC1-7):H03K3/00 |
主分类号 |
G05F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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