发明名称 LOGIC ARRANGEMENT, SYSTEM AND METHOD FOR AUTOMATIC GENERATION AND SIMULATION OF A FIELDBUS NETWORK LAYOUT
摘要 The present invention relates generally to a logic arrangement, system and method which aid in the design of a fieldbus network. In particular, the logic arrangement, system and method facilitate a generation of a fieldbus network layout in accordance with a fieldbus network design and the design rules of the particular fieldbus protocol. Further, the logic arrangement, system and method can facilitate a computer simulation of an operation of a designed fieldbus network prior to its physical implementation.
申请公布号 WO2004054160(A2) 申请公布日期 2004.06.24
申请号 WO2003US39277 申请日期 2003.12.10
申请人 SMAR RES CORP 发明人 CASSIOLATO CESAR
分类号 G05B19/418;G06F17/00;G06F17/50;G06G7/62;H04L;H04L12/24;H04L12/40 主分类号 G05B19/418
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