发明名称 SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To save failures produced after assembling process, using an inexpensive tester. SOLUTION: An error detection circuit 13 compares read data from a memory cell with data from an external I/O terminal 12 by a comparator circuit 18 for deciding the quality of the memory cell. The error detection circuit 13 outputs a detection signal COMPRERR, when the memory cell is of poor quality. A self-fused program circuit 20 receives the detection signal COMPERR for latching to a latch circuit LAi with an external address as a relief address. A counter Ci and a switching circuit SW transfer the relief address latched by the latch circuit LAi to a fuse program circuit FPi one bit by one bit, thus programming the relief address. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004178674(A) 申请公布日期 2004.06.24
申请号 JP20020342897 申请日期 2002.11.26
申请人 TOSHIBA MICROELECTRONICS CORP;TOSHIBA CORP 发明人 KOZUKA EIJI
分类号 G11C29/04;G11C7/10;G11C29/00;G11C29/12;(IPC1-7):G11C29/00 主分类号 G11C29/04
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