| 摘要 |
A method and apparatus for reducing power dissipation during a scan operation during testing of digital logic circuits which provides for scanning data while switching a limited number of nodes during scan-in and scan-out of input and result chains, and which isolates the logic circuit from random stimulation by scan chains as they are scanned. A scan chain includes a plurality of level sensitive scan design LSSD scan latches, each comprising a master latch M and a slave latch S. The master latch has a first input port D used for operation in a functional mode, and a second input port S used for operation in a scan mode, a scan enable input port, and a clock input port. The master latch M produces output scan data Sout which is directed to a slave latch S which produces a data output Q for the logic circuit under test.
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