发明名称 PHASE LOCKED LOOP APPARATUS AND PHASE LOCKED LOOP METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a PLL apparatus for maintaining a phase lock state so as to prevent an output frequency from being fluctuated even when a reference signal for phase comparison is momentarily interrupted. <P>SOLUTION: The PLL apparatus for controlling a control object signal is provided with: a reference signal input section 13 for receiving the reference signal 6, allowing a delay circuit 7 to generate a delayed reference signal 12 resulting from delaying the reference signal 6 by a prescribed time, and allowing an OR circuit 8 to generate an OR between the reference signal 6 and the delayed reference signal 12 as an adjusted reference signal 14; a phase comparator 1 for comparing the adjusted reference signal 14 with the control object signal to detect a phase difference between them; a charge pump 2 for receiving the phase difference and supplying a current to a loop filter 3 according to the received phase difference; the loop filter 3 for storing the supplied current and converting the stored current into a voltage; a VCO 4 for generating a signal with a frequency based on the voltage; and a frequency divider 5 for receiving the signal generated by the VCO 4 and frequency-dividing the signal to be supplied to the phase comparator 1 as the control object signal. <P>COPYRIGHT: (C)2004,JPO
申请公布号 JP2004179719(A) 申请公布日期 2004.06.24
申请号 JP20020340474 申请日期 2002.11.25
申请人 MITSUBISHI ELECTRIC CORP 发明人 INOUE TAKEHIRO
分类号 H03L7/14;H03L7/08 主分类号 H03L7/14
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