| 摘要 |
PROBLEM TO BE SOLVED: To monitor not only erroneous monitor by bit units but also data loss by frame units between the input/output of an FIFO memory by a simple circuit. SOLUTION: At the writing side of an FIFO memory 2, a parity generating part 1 alternately generates odd-numbered parity/even-numbered parity for each frame. The written data and the alternating odd-numbered/even-numbered parity generation results are written in an FIFO memory 2. At the reading side of the FIFO memory 2, parity check is operated by a parity calculating part 3, and a parity error by frame units is checked by a frame loss detecting part 4. When the loss of the frame data is generated due to the abnormal operation of the FIFO memory, the parity arithmetic system of read data is no longer odd-numbered/even-numbered alternating, and any parity error by frame units is generated, and the frame loss can be detected as a result. When the frame loss is detected, the forced switching of the reading side frame clocks 1 and 2 is operated by an odd number/even number switching part 5, and the odd number/even number alternating at the writing side and the reading side is re-synchronized. COPYRIGHT: (C)2004,JPO
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